Tao Research Summary Page

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Title:

Abstract:

  • Thesis (zip -- 303K)
  • Thesis (pdf -- 405K)
  • Thesis Proposal Introduction
  • Pictures
  • Top side of a reconfigurable macrofunction unit (RMU) card that I built for Tao. Each processor node consists of one of these RMU cards.

    Bottom side of an RMU.

  • Top view of the entire Tao motherboard with 4 RMUs and an RE SSRAM card (big file!).
  • Bottom view of the same (big file!).
  • Dataflow in the Tao

    This links to a diagram of the routing architecture of Tao.

    Introduction to thesis proposal:

    The conventional paradigm of computation, embodied by the ideas of Church and Turing and embedded in the stored-program (von Neumann) architecture, formulates the dichotomy of hardware and software. Hardware is the structure of the computer; it is immutable and tangible, like the Turing tape reader. Software is the purpose of the computer; it is volatile and intangible, like the bits of data on the infinite Turing tape. Excluded from this paradigm is the possibility of modifying the structure to suit the purpose. As a result, contemporary computer architectures exhibit optimizations such as multiple bus standards for different purposes, branch prediction, and complex memory coherency protocols for multiprocessor architectures. However, if hardware could be modified (reconfigured) to suit the purpose, one can imagine a computer with a single all-in-one expansion socket, and processors would not need branch prediction or coherence protocols. Indeed, thanks to programmable logic technology, this traditional paradigm can be replaced with something new. With programmable logic, structure can be modified for a specific purpose, resulting in a dramatic increase of performance. A new genre of computer must be defined: a computer without a stored-program architecture that can be customized to any algorithm, including a Turing Machine. For this computer, the architecture becomes the program. Others who have studied such machines have referred to them as either virtual computers, custom computers, programmable active memories, functional memories, or transformable computers. I shall use the common term reconfigurable computer.

    How is it that the same piece of hardware can be reconfigured to perform multiple software-like tasks? The enabling technology of programmable logic is based on the premise that the functionality of hardware lies in the way primitive elements are connected. Thus, given a sufficiently large set of primitive sequential and combinatorial elements and a reconfigurable interconnect, a vast number of functions can be implemented with the same hardware.

    Researchers have been quick to implement reconfigurable computers, lured by the promise of fast computation. However, describing an algorithm in hardware is an arduous task, and performance is often times disappointing because the underlying structure of the programmable logic contains inherent weaknesses. For reasons involving cost, performance, and engineering difficulty, a high-end workstation is often preferable to a reconfigurable computer. Although programmable logic is capable of implementing any computation, it is not capable of efficiently implementing all useful functions due to inherent architectural weaknesses. These limitations can be overcome, in part, if proper hardware support is provided. In addition, it is easier to create applications for reconfigurable computer designs if certain architectural tradeoffs are applied. This work will explore the possibilities of architecturally assisted reconfigurable computing.

    [snip to later in document]

    A well-balanced system is the grail of all computer architects; caches, pipelines, interleaving, register renamingóthey are all elements of a well balanced system. Without such features, the processor core will starve and system performance will never reach the theoretical peak performance of the processor. Reconfigurable processors promise an even greater performance than traditional processors, placing an even greater demand upon the system. In the spirit of the balance represented by the Taoist Ying-Yang symbol, I have named my design Tao.

    Tao is a systolic array of reconfigurable processors augmented with tightly coupled SRAM, embedded in rich routing resources, all on a single PCI card. Tao will be a holistically balanced systemódeficiencies at one level will be compensated for at another level. Tao will be accessible by end users via the datfile interface, chosen for its popularity among MIT researchers and its existing base of applications. In order to demonstrate Tao, datfile code will be profiled for a commonly used, compute intensive routine; this routine will be implemented in Tao.

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